EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 764

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

3–10
Sharing ATX PLLs
Combining Receiver Only Channels
Stratix IV Device Handbook Volume 2: Transceivers
1
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The Quartus II software allows you to share the same ATX PLL for multiple
transceiver instances if the following requirements are met:
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You can selectively use the receiver in the transceiver channel by selecting the
Receiver only configuration in the What is the Operating Mode? option on the
General screen of the ALTGX MegaWizard Plug-In Manager.
You can combine Receiver only channel instances of different configurations and data
rates into the same transceiver block. Because each receiver channel contains its own
dedicated CDR, each Receiver only instance (assuming one receiver channel per
instance) can have a different data rate.
For the Quartus II software to combine the Receiver only instances within the same
transceiver block, you must connect gxb_powerdown (if used) for all the channel
instances to the same logic or input pin. For more information, refer to
Requirements to Combine Channels” on page
If your design contains a Receiver only instance, the Quartus II software disables all
the settings for the unused transmitter channel present in the same physical
transceiver channel. Therefore, the unused transmitter channel is always powered
down in the hardware.
The ATX PLL bandwidth in both instances are the same
If the selected functional mode in one instance is (OIF) CEI Phy Interface or PCIe,
the other functional modes must be the same to share the ATX PLL. For example, if
you have two channels, one configured in Basic mode and the other configured in
(OIF) CEI Phy Interface mode at the same data rate, the Quartus II software does
not share the same PLL because the internal parameters for these two functional
modes are different.
The base data rate and effective data rate values are the same.
The pll_powerdown port in the instances are connected to the same logic.
The instances are placed on the same side of the device.
There is no contention on the ×N clock lines from the ATX PLL and the two
instances.
1
For more information about ×N clocking, refer to the “Transmitter Channel
Data Path Clocking” section in the
chapter.
Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Transceiver Clocking in Stratix IV Devices
3–3.
February 2011 Altera Corporation
“General
Sharing ATX PLLs