EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 481

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
February 2011 Altera Corporation
Figure 1–33. AC-Coupled Link
The following protocols supported by Stratix IV GX and GT devices mandate
AC-coupled links:
■
■
■
■
■
Stratix IV GT devices allow the high-speed links to be AC-coupled for the entire data
rate range between 600 Mbps and 11.3 Gbps.
In a DC-coupled link, the transmitter DC V
The link V
off-chip receiver termination and biasing circuitry must ensure compatibility between
the transmitter and receiver V
PCIe
Gigabit Ethernet
Serial RapidIO
XAUI
SDI
DC-Coupled Links
Transmitter
CM
TX Termination
depends on the transmitter V
TX
V
CM
CM
.
Figure 1–34
Physical Medium
Physical Medium
CM
CM
is seen unblocked at the receiver buffer.
shows a DC-coupled link.
and the receiver V
AC Coupling
Capacitor
AC Coupling
Capacitor
Stratix IV Device Handbook Volume 2: Transceivers
RX
V
CM
RX Termination
CM
Receiver
. The on-chip or
1–37