EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 500

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

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Stratix IV Device Handbook Volume 2: Transceivers
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In LTD mode, the CDR uses a phase detector to keep the recovered clock
phase-matched to the data. If the CDR does not stay locked to data due to frequency
drift or severe amplitude attenuation, the LTR/LTD controller switches the CDR back
to LTR mode to lock to the input reference clock. In automatic lock mode, the
LTR/LTD controller switches the CDR from LTD to LTR mode when the following
conditions are met:
■
■
The switch from LTD to LTR mode is indicated by the de-assertion of the
rx_freqlocked signal.
In automatic lock mode, the LTR/LTD controller relies on the PPM detector and the
phase relationship detector to set the CDR in LTR or LTD mode. The PPM detector
and phase relationship detector reaction times can be too long for some applications
that require faster CDR lock time. You can manually control the CDR to reduce its lock
time using the rx_locktorefclk and rx_locktodata ports. In manual lock mode, the
LTR/LTD controller sets the CDR in LTR or LTD mode depending on the logic level
on the rx_locktorefclk and rx_locktodata signals.
When the rx_locktorefclk signal is asserted high, the LTR/LTD controller forces the
CDR to lock to the reference clock. When the rx_locktodata signal is asserted high, it
forces the CDR to lock to data. When both signals are asserted, the rx_locktodata
signal takes precedence over the rx_locktorefclk signal, forcing the CDR to lock to
data.
When the rx_locktorefclk signal is asserted high, the rx_freqlocked signal does not
have any significance and is always driven low, indicating that the CDR is in LTR
mode. When the rx_locktodata signal is asserted high, the rx_freqlocked signal is
always driven high, indicating that the CDR is in LTD mode. If both signals are de-
asserted, the CDR is in automatic lock mode.
The Altera-recommended transceiver reset sequence varies depending on the CDR
lock mode.
For more information about reset sequence recommendations, refer to the
Control and Power Down in Stratix IV Devices
As silicon progresses towards smaller process nodes, the performance of circuits at
these smaller nodes depends more on process variations. These process variations
result in analog voltages that can be offset from the required ranges. Offset
cancellation logic corrects these offsets. The receiver buffer and receiver CDR require
offset cancellation.
Signal threshold detection circuitry indicates the absence of valid signal levels at
the receiver input buffer
■
The CDR output clock is not within the configured PPM frequency threshold
setting with respect to the input reference clock
Offset Cancellation in the Receiver Buffer and Receiver CDR
Valid for PCIe mode only. This condition is defaulted to true for all other
modes.
Manual Lock Mode
Chapter 1: Transceiver Architecture in Stratix IV Devices
chapter.
February 2011 Altera Corporation
Transceiver Block Architecture
Reset