EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 749

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 2: Transceiver Clocking in Stratix IV Devices
Configuration Examples
Table 2–19. Quartus II Assignments
February 2011 Altera Corporation
From
To
Assignment Name
Value
Note to
(1) This is an example design hierarchy path for the tx_clkout[4] signal.
Table
Configuration Example 3: Configuring Sixteen Channels Across Four
Transceiver Blocks
2–19:
1
Table 2–19
scheme shown in
This example relates to
Clock” on page
Figure 2–40
transceiver blocks. The incoming serial data to all 16 channels has a 0 PPM frequency
difference with respect to each other. The rx_coreclk ports of all 16 channels are
connected together and driven by rx_clkout[9] in transceiver block GXBR2.
rx_clkout[9] also clocks the receiver data and status signals of all 16 channels in the
FPGA fabric. With this clocking scheme, only one global, regional, or global and
regional clock resource is used by rx_clkout[9].
top_level/top_xcvr_instance1/altgx_component/tx_clkout[4]
tx_dataout[15..0]
GXB 0 PPM Core Clock Setting
ON
lists the Quartus II assignments that you must make for the clocking
shows 16 non-bonded channels without rate matcher located across four
2–69.
Figure
“User-Selected Receiver Phase Compensation FIFO Read
2–38.
Stratix IV Device Handbook Volume 2: Transceivers
(1)
2–77