EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 1025

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
Implementation and Integration
February 2011 Altera Corporation
Create Transceiver Instances
Create Dynamic Reconfiguration Controller Instances
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The ALTGX MegaWizard Plug-In Manager to creates the transceiver instance. In the
architecture phase, you identified the transceiver configuration for your design. Using
the ALTGX MegaWizard Plug-In Manager, select the appropriate parameters that
apply to your architecture requirements.
Reset and Status Signals
The ALTGX MegaWizard Plug-In Manger provides various reset and status signals:
If you determine that your application requires dynamic reconfiguration, select the
options in the Reconfig screen of the ALTGX MegaWizard interface.
If you intend to dynamically reconfigure the channel into other protocol modes or
data rates, the Reconfig screen provides multiple options (for example, the channel
interface and Use alternate PLL options) to enable this feature.
To understand the logical channel addressing, logical PLL index, and type of
reconfiguration to select options in the Reconfig screen, refer to the “Channel and
CMU PLL Reconfiguration Mode Details” section in the
Stratix IV Devices
Depending on your system, when you use multiple transceiver channels, you might
be able to share the transmitter and receiver parallel clocks of one channel with the
other channels. If your design requires sharing a clock resource, select the tx_coreclk
and rx_coreclk ports.
Transceiver-FPGA fabric interface clock sharing conditions are provided in the
Transceiver Clocking in Stratix IV Devices
For more information about using the ALTGX MegaWizard Plug-In Manager and the
functionality of the different options and signals available, refer to the
Transceiver Setup Guide for Stratix IV Devices
Use the ALTGX_RECONFIG MegaWizard interface to create the dynamic
reconfiguration controller instance. If you intend to use the channel and CMU PLL
reconfiguration feature, select the relevant options in the ALTGX_RECONFIG
Megawizard Plug-In Manager.
For descriptions of the options in the ALTGX_RECONFIG megafunction, refer to the
ALTGX_RECONFIG Megafunction User Guide for Stratix IV Devices
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Reset signals—tx_digitalreset, rx_digitalreset, rx_analogreset, and
pll_powerdown are required to reset the transceiver PCS and PMA functional
blocks.
Status signals—rx_freqlocked and pll_locked indicate the state of the
receiver CDR and transmitter PLL, respectively. Use these reset and status
signals to implement the transceiver reset control logic in the FPGA fabric. For
more information, refer to
chapter.
“Create Reset and Control Logic” on page
chapter.
chapter.
Dynamic Reconfiguration in
Stratix IV Device Handbook Volume 3
chapter.
ALTGX
2–8.
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