EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 748

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

2–76
Figure 2–39. Sixteen Identical Channels Across Four Transceiver Blocks for Configuration Example 2
Stratix IV Device Handbook Volume 2: Transceivers
Configuration Example 2: Configuring Sixteen Identical Channels Across
Four Transceiver Blocks
1
This example relates to
Clock” on page
Figure 2–39
blocks. The tx_coreclk ports of all 16 transmitter channels are connected together
and driven by the tx_clkout[4] signal from channel 0 in transceiver block GXBR1. The
tx_clkout[4] signal also drives the transmitter data and control logic of all 16
transmitter channels in the FPGA fabric. With this clocking scheme, only one global
clock resource is used by the tx_clkout[4] signal.
Channel [15:12]
Channel [11:8]
Channel [3:0]
Channel [7:4]
and Control
and Control
and Control
and Control
TX Data
shows 16 identical transmitter channels located across four transceiver
TX Data
TX Data
TX Data
FPGA
Fabric
Logic
Logic
Logic
Logic
2–69.
tx_coreclk[15:12]
tx_coreclk[7:4]
tx_coreclk[11:8]
tx_coreclk[3:0]
“User-Selected Receiver Phase Compensation FIFO Read
tx_clkout[12]
tx_clkout[4]
tx_clkout[8]
tx_clkout[0]
Transceiver Block GXBR3
Transceiver Block GXBR2
Transceiver Block GXBR0
Transceiver Block GXBR1
Chapter 2: Transceiver Clocking in Stratix IV Devices
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
February 2011 Altera Corporation
Configuration Examples