EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 427

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 13: Power Management in Stratix IV Devices
Stratix IV External Power Supply Requirements
Stratix IV External Power Supply Requirements
April 2011 Altera Corporation
f
f
The Quartus II software sets unused device resources in the design to low-power
mode to reduce static and dynamic power. It also sets the following resources to
low-power mode when they are not used in the design:
■
■
■
If a phase-locked loop (PLL) is instantiated in the design, asserting the areset pin
high keeps the PLL in low-power mode.
Table 13–1
considerations can add to the permutations to give you flexibility in designing your
system.
Table 13–1. Programmable Power Capabilities in Stratix IV Devices
This section describes the different external power supplies required to power
Stratix IV devices. You can supply some of the power supply pins with the same
external power supply, provided they have the same voltage level.
For power supply pin connection guidelines and power regulator sharing, refer to the
Stratix IV GX and Stratix IV E Device Family Pin Connection
For each Altera recommended power supply’s operating conditions, refer to the
and Switching Characteristics for Stratix IV Devices
Note to
(1) Tiles with DSP blocks and memory blocks that are used in the design are always set to high-speed mode. By
LABs and MLABs
TriMatrix memory blocks
DSP blocks
default, unused DSP blocks and memory blocks are set to low-power mode.
Table
lists the available Stratix IV programmable power capabilities. Speed grade
13–1:
Global Clock Networks
Memory Blocks
DSP Blocks
Feature
Routing
LAB
chapter.
Programmable Power Technology
Fixed setting
Fixed setting
Guidelines.
Stratix IV Device Handbook Volume 1
Yes
Yes
No
(1)
(1)
DC
13–3