EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 342

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

10–8
Stratix IV Device Handbook Volume 1
1
You can also synchronize initialization of multiple devices or delay initialization with
the CLKUSR option. You can turn on the Enable user-supplied start-up clock
(CLKUSR) option in the Quartus II software from the General tab of the Device and
Pin Options dialog box. Supplying a clock on CLKUSR does not affect the configuration
process. The CONF_DONE pin goes high one byte early in FPP modes. The last byte is
required for FPP mode. After the CONF_DONE pin transitions high, CLKUSR is enabled
after the time specified at t
require 8,532 clock cycles to initialize properly and enter user mode. Stratix IV devices
support a CLKUSR f
An optional INIT_DONE pin is available, which signals the end of initialization and the
start of user-mode with a low-to-high transition. This Enable INIT_DONE Output
option is available in the Quartus II software from the General tab of the Device and
Pin Options dialog box. If you use the INIT_DONE pin, it is high because of an external
10-kΩ pull-up resistor when nCONFIG is low and during the beginning of
configuration. After the option bit to enable INIT_DONE is programmed into the device
(during the first frame of configuration data), the INIT_DONE pin goes low. When
initialization is complete, the INIT_DONE pin is released and pulled high. The MAX II
device must be able to detect this low-to-high transition, which signals the device has
entered user mode. When initialization is complete, the device enters user mode. In
user-mode, the user I/O pins no longer have weak pull-up resistors and function as
assigned in your design.
Two DCLK falling edges are required after CONF_DONE goes high to begin the
initialization of the device for both uncompressed and compressed bitstream in FPP.
To ensure DCLK and DATA[7..0] are not left floating at the end of configuration, the
MAX II device must drive them either high or low, whichever is convenient on your
board. The DATA[7..0] pins are available as user I/O pins after configuration. When
you select the FPP scheme as a default in the Quartus II software, these I/O pins are
tri-stated in user mode. To change this default option in the Quartus II software, select
the Dual-Purpose Pins tab of the Device and Pin Options dialog box.
The configuration clock (DCLK) speed must be below the specified frequency to ensure
correct configuration. No maximum DCLK period exists, which means you can pause
configuration by halting DCLK for an indefinite amount of time.
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
M AX
of 125 MHz.
CD2CU
. After this time period elapses, Stratix IV devices
Fast Passive Parallel Configuration
April 2011 Altera Corporation