EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 620

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–176
Figure 1–143. SONET/SDH OC-96 Datapath
Stratix IV Device Handbook Volume 2: Transceivers
tx_coreclk
rx_coreclk
FPGA
Fabric
FPGA Fabric-Transmitter
SONET/SDH OC-96 Datapath
Figure 1–143
mode.
SONET/SDH Transmission Bit Order
Unlike Ethernet, where the LSB of the parallel data byte is transferred first,
SONET/SDH requires the MSB to be transferred first and the LSB to be transferred
last. To facilitate the MSB-to-LSB transfer, you must enable the following options in
the ALTGX MegaWizard Plug-In Manager:
■
■
Depending on whether data bytes are transferred MSB-to-LSB or LSB-to-MSB, you
must select the appropriate word aligner settings in the ALTGX MegaWizard Plug-In
Manager.
transmission order.
Word Alignment
The word aligner in SONET/SDH OC-12, OC-48, and OC-96 modes is configured in
manual alignment mode, as described in
8-Bit PMA-PCS Interface Modes” on page
In OC-12 and OC-48 configurations, you can configure the word aligner to either align
to a 16-bit A1A2 pattern or a 32-bit A1A1A2A2 pattern. This is controlled by the
rx_a1a2size input port to the transceiver. A low level on the rx_a1a2size port
configures the word aligner to align to a 16-bit A1A2 pattern; a high level on the
rx_a1a2size port configures the word aligner to align to a 32-bit A1A1A2A2 pattern.
In OC-96 configuration, the word aligner is only allowed to align to a A1A1A2A2
pattern, so the input port rx_ala2size is unavailable. Barring this difference, the
OC-96 word alignment operation is similar to that of the OC-12 and OC-48
configurations.
FPGA Fabric-Receiver
Interface Clock
Flip transmitter input data bits
Flip receiver output data bits
Interface Clock
Table 1–65 on page 1–177
shows the transceiver datapath when configured in SONET/SDH OC-96
tx_clkout
rx_clkout
Compensation
RX Phase
FIFO
Compensation
wrclk
TX Phase
FIFO
rdclk
wrclk
Serializer
Transmitter Channel PCS
Byte De-
serializer
Byte
/2
lists the correct word aligner settings for each bit
/2
Low-Speed Parallel Clock
Receiver Channel PCS
rdclk
“Word Aligner in Single-Width Mode with
1–60.
Recovered Clock
Chapter 1: Transceiver Architecture in Stratix IV Devices
Parallel
Aligner
Word
Receiver Channel PMA
Transmitter Channel PMA
Serializer
De-
Serializer
Divider
Clock
Local
February 2011 Altera Corporation
CDR
High-Speed
Serial Clock
Transceiver Block Architecture