EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 470

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–26
Figure 1–21. 8B/10B Conversion Format in Double-Width Mode
Figure 1–22. Encoded Control Word and Data Word Transmission
Stratix IV Device Handbook Volume 2: Transceivers
CTRL[1:0]
MSB
19
tx_ctrlenable[1:0]
j ' h '
tx_datain[15:0]
18
code group
g '
17
In double-width mode, the tx_ctrlenable[1:0] port is used to identify which 8-bit
data is to be encoded as a control word. The lower bit, tx_ctrlenable[0], is
associated with the LSByte; the upper bit, tx_ctrlenable[1], is associated with the
MSByte. When tx_ctrlenable is low, the byte at the tx_datain port of the transceiver
is encoded as data (Dx.y); otherwise, it is encoded as a control code (Kx.y).
Figure 1–22
a control code because tx_ctrlenable[0] is high in the second clock cycle.
The 8B/10B encoder does not check to see if the code word entered is one of the 12
valid control code groups specified in the IEEE 802.3 8B/10B encoder specification. If
an invalid control code is entered, the resulting 10-bit code may be encoded as an
invalid code (it does not map to a valid Dx.y or Kx.y code), or unintended valid Dx.y
code, depending on the value entered.
The following is an example of an invalid control word encoded into a valid Dx.y
code. With an encoding invalid code K24.1 (tx_datain = 8'h38 + tx_ctrl = 1'b1),
depending on the current running disparity, the K24.1 can be encoded as
10'b0110001100 (0 × 18C), which is equivalent to a D24.6+ (8'hD8 from the RD+
column). An 8B/10B decoder can decode this and not assert a code error flag.
clock
15
H '
Control Code Encoding
f '
16
14
G ' F ' E ' D ' C ' B ' A '
15
i'
13
D3.4
e '
shows that only the lower byte of the tx_datain[15:0] port is encoded as
14
12
8378
0
Cascaded 8B/10B Conversion
d '
13
11
D24.3
c '
12
10
b '
11
D28.5
9
a '
10
BCBC
8
1
j
9
K28.5
H
7
h
8
G
6
g
7
F
D15.0
5
Chapter 1: Transceiver Architecture in Stratix IV Devices
f
0F00
6
E
4
i
5
D
D0.0
3
0
e
4
C
2
d
3
D31.5
B
1
February 2011 Altera Corporation
c
2
BF3C
A
0
Transceiver Block Architecture
b
Parallel Data
1
D28.1
LSB
a
0