EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 361

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Passive Serial Configuration
April 2011 Altera Corporation
1
When nCONFIG goes high, the device comes out of reset and releases the open-drain
nSTATUS pin, which is then pulled high by an external 10-kΩpull-up resistor. After
nSTATUS is released, the device is ready to receive configuration data and the
configuration stage begins. When nSTATUS is pulled high, the MAX II device places
the configuration data one bit at a time on the DATA0 pin. If you are using
configuration data in .rbf, .hex, or .ttf format, you must send the LSB of each data byte
first. For example, if the .rbf contains the byte sequence 02 1B EE 01 FA, the serial
bitstream you must transmit to the device is
0100-0000 1101-1000 0111-0111 1000-0000 0101-1111.
The Stratix IV device receives configuration data on the DATA0 pin and the clock is
received on the DCLK pin. Data is latched into the device on the rising edge of DCLK.
Data is continuously clocked into the target device until CONF_DONE goes high. After
the device has received all configuration data successfully, it releases the open-drain
CONF_DONE pin, which is pulled high by an external 10-kΩ pull-up resistor. A
low-to-high transition on CONF_DONE indicates configuration is complete and
initialization of the device can begin. The CONF_DONE pin must have an external 10-kΩ
In Stratix IV devices, the initialization clock source is either the internal oscillator or
the optional CLKUSR pin. By default, the internal oscillator is the clock source for
initialization. If you use the internal oscillator, the Stratix IV device provides itself
with enough clock cycles for proper initialization. Therefore, if the internal oscillator
is the initialization clock source, sending the entire configuration file to the device is
sufficient to configure and initialize the device. Driving DCLK to the device after
configuration is complete does not affect device operation.
You also have the flexibility to synchronize initialization of multiple devices or to
delay initialization with the CLKUSR option. You can turn on the Enable user-supplied
start-up clock (CLKUSR) option in the Quartus II software from the General tab of
the Device and Pin Options dialog box. If you supply a clock on CLKUSR, it will not
affect the configuration process. After all configuration data has been accepted and
CONF_DONE goes high, CLKUSR is enabled after the time specified at t
time period elapses, Stratix IV devices require 8,532 clock cycles to initialize properly
and enter user mode. Stratix IV devices support a CLKUSR f
An optional INIT_DONE pin is available that signals the end of initialization and the
start of user-mode with a low-to-high transition. The Enable INIT_DONE Output
option is available in the Quartus II software from the General tab of the Device and
Pin Options dialog box. If you use the INIT_DONE pin, it is high due to an external
10-kΩ pull-up resistor when nCONFIG is low and during the beginning of
configuration. After the option bit to enable INIT_DONE is programmed into the device
(during the first frame of configuration data), the INIT_DONE pin goes low. When
initialization is complete, the INIT_DONE pin is released and pulled high. The MAX II
device must be able to detect this low-to-high transition that signals the device has
entered user mode. When initialization is complete, the device enters user mode. In
user-mode, the user I/O pins no longer have weak pull-up resistors and function as
assigned in your design.
Two DCLK falling edges are required after CONF_DONE goes high to begin the
initialization of the device for both uncompressed and compressed bitstream in PS.
pull-up resistor for the device to initialize.
MAX
Stratix IV Device Handbook Volume 1
of 125 MHz.
CD2CU
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