EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 1021

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
Architecture
Architecture
February 2011 Altera Corporation
Device Specification
Transceiver Configuration
f
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The first step in creating a transceiver-based design is to map your system
requirements with the Stratix IV GX device supported features. The Stratix IV GX
device contains multiple transceiver channels that you can configure in multiple data
rates and protocols. It also provides multiple transceiver clocking options. For your
design, identify the transceiver capabilities and clocking options to ensure that the
transceiver meets your system requirements.
This section describes the critical parameters that you need to identify as part of this
architecture phase.
The following device specifications must meet your requirements:
■
■
■
For information about device characteristics, refer to the “Transceiver Performance
Specifications” section in the
chapter. For information about transceiver resources, refer to the
Family Overview
Use the ALTGX MegaWizard
transceiver channel’s features and options.
When selecting a transceiver configuration, check for the following parameters:
■
For more information about transceiver specifications, refer to the “Transceiver
Performance Specifications” section of the
Stratix IV Devices
■
Refer to the device data sheet to ensure that the transceivers meet the data rate and
electrical requirements for your target high-speed interface application; for
example, the jitter specification and voltage output differential (V
Check whether the device family that you select supports your design
requirements; for example, the number of transceiver channels, FPGA logic
density, memory elements, and DSP blocks.
If you intend to migrate to a higher logic density or higher transceiver count
device in the future, ensure that the migration device is available.
Check whether the transceiver physical coding sublayer (PCS) and physical
medium attachment (PMA) functional blocks comply with your system
requirements. For example, check whether the rate match (clock rate
compensation) FIFO in the receiver channel PCS meets the parts per million (PPM)
specifications required for your application.
Select a configuration that meets your latency requirements. If your system has
maximum latency requirements through the transceiver data path, consider the
appropriate functional configuration. The Stratix IV GX transceiver supports
various configurations that differ in latency (for example, low latency PCS mode
and Basic [PMA direct] mode).
chapter.
chapter.
DC and Switching Characteristics for Stratix IV Devices
™
Plug-In Manager interface to configure the Stratix IV
DC and Switching Characteristics for
Stratix IV Device Handbook Volume 3
Stratix IV Device
OD
) range.
2–3