EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 173

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

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SIV51006-3.2
Stratix IV Device Handbook Volume 1
February 2011
February 2011
SIV51006-3.2
This chapter describes how Stratix
you to work in compliance with current and emerging I/O standards and
requirements. With these device features, you can reduce board design interface costs
and increase development flexibility.
Altera
power efficiency for high-end applications, allowing you to innovate without
compromise. Stratix IV I/Os are specifically designed for ease-of-use and rapid
system integration while simultaneously providing the high bandwidth required to
maximize internal logic capabilities and produce system-level performance.
Stratix IV device I/O capability far exceeds the I/O bandwidth available from
previous generation FPGAs. Independent modular I/O banks with a common bank
structure for vertical migration lend efficiency and flexibility to the high-speed I/O.
Package and die enhancements with dynamic termination and output control provide
best-in-class signal integrity. Numerous I/O features assist high-speed data transfer
into and out of the device, including:
■
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Up to 32 full-duplex clock data recovery (CDR)-based transceivers supporting
data rates between 600 Mbps and 8.5 Gbps
Dedicated circuitry to support physical layer functionality for popular serial
protocols, such as PCI Express
(GbE), Serial RapidIO
SD/HD/3G-SDI, Fibre Channel, SFI-5, and Interlaken
Complete PCIe protocol solution with embedded PCIe hard IP blocks that
implement PHY-MAC layer, data link layer, and transaction layer functionality
Single-ended, non-voltage-referenced, and voltage-referenced I/O standards
Low-voltage differential signaling (LVDS), reduced swing differential signaling
(RSDS), mini-LVDS, high-speed transceiver logic (HSTL), and SSTL
Single data rate (SDR) and half data rate (HDR—half frequency and twice data
width of SDR) input and output options
Up to 132 full duplex 1.6 Gbps true LVDS channels (132 Tx + 132 Rx) on the row
I/O banks
Hard dynamic phase alignment (DPA) block with serializer/deserializer
(SERDES)
Deskew, read and write leveling, and clock-domain crossing functionality
Programmable output current strength
Programmable slew rate
Programmable delay
Programmable bus-hold circuit
®
Stratix IV FPGAs deliver a breakthrough level of system bandwidth and
®
, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G,
6. I/O Features in Stratix IV Devices
®
®
(PIPE) (PCIe) Gen1 and Gen2, Gigabit Ethernet
IV devices provide I/O capabilities that allow
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