EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 728

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

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Stratix IV Device Handbook Volume 2: Transceivers
Limitations of the Quartus II Software-Selected Transmitter Phase Compensation FIFO Write
Clock
The Quartus II software uses a single tx_clkout signal to clock the transmitter phase
compensation FIFO write port of all identical channels within a transceiver block.
This results in one global and/or regional clock resource being used for each group of
identical channels within a transceiver block.
For identical channels located across the transceiver blocks, the Quartus II software
does not use a single tx_clkout signal to clock the write port of the transmitter phase
compensation FIFOs for all channels. It uses one tx_clkout signal for each group of
identical channels per transceiver block. This results in higher global and regional
clock resource usage.
Example 4: Sixteen Identical Channels Across Four Transceiver Blocks
Figure 2–31
blocks. The Quartus II software uses tx_clkout from Channel 0 in each transceiver
block to clock the write port of the transmitter phase compensation FIFO in all four
channels in that transceiver block. This results in four global and/or regional clock
resources being used, one for each transceiver block.
shows 16 identical transmitter channels located across four transceiver
Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric-Transceiver Interface Clocking
February 2011 Altera Corporation