EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 927

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Controller Port List
Table 5–16. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 6 of 13)
February 2011 Altera Corporation
Analog Settings Control/Status Signals
tx_vodctrl[2:0]
Port Name
(1)
Output
Input/
Input
This is an optional transmit buffer V
transmitter channel. The number of settings varies based on the
transmit buffer supply setting and the termination resistor setting
on the TX Analog screen of the ALTGX MegaWizard Plug-In
Manager.
The width of this signal is fixed to 3 bits if you enable either the Use
'logical_channel_address' port for Analog controls
reconfiguration option or the Use same control signal for all the
channels option in the Analog controls screen. Otherwise, the
width of this signal is 3 bits per channel.
For more information, refer to
Controls” on page
The following shows the V
tx_vodctrl settings for 100-Ω termination.
For more information, refer to the “Programmable Output
Differential Voltage” section of the
Stratix IV Devices
tx_vodctrl[2:0]
3’b000
3’b001
3’b010
3’b011
3’b100
3’b101
3’b110
3’b111
chapter.
5–13.
Stratix IV Device Handbook Volume 2: Transceivers
OD
V
Description
OD
values corresponding to the
“Dynamically Reconfiguring PMA
(mV) for 1.4 V V
Transceiver Architecture in
200
400
600
700
800
900
1000
1200
OD
control signal. It is 3 bits per
CCH
(Note
3),
(4)
5–81