EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 1034

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

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Stratix IV Device Handbook Volume 3
Guidelines to Debug System Level Issues
If you have determined that the logic in the FPGA fabric is functionally correct, check
for system level issues:
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Check the voltage ripple across the 2 kΩ resistor that is connected to the RREF pin.
The voltage ripple must be less than 60 mv.
Measure the eye on the near-end and far-end of the transmitter to understand the
jitter added by the transmitter and interconnect.
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Measure signals on the traces (no connector) using a high-impedance differential
probe with short leads.
Ensure that characteristic impedance on the interconnect matches the source and
load systems.
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Compensate for high frequency losses in the interconnect by changing the
equalization settings of the Stratix IV GX device and check for improvement of the
bit error rate. If the upstream system does not have an equalization feature,
increase the pre-emphasis (1st post tap) of the Stratix IV GX transmitter. In cases
where there are multiple interconnects between the Stratix IV GX device and the
upstream system, use the pre-tap and 2nd post tap. Altera provides tools to select
the pre-emphasis.
Ensure that the high-speed scopes you use for measurement have sufficient
bandwidth (the bandwidth rating on the scope and cables must be at least
three times the serial data rate).
Check whether the eye meets the eye-mask requirements if specified by the
protocol application.
Use scopes that provide information on the different jitter components to
understand the possible source of the increased jitter. For example, increased
intersymbol interface (ISI) indicates potential bandwidth limitations on the
interconnect.
Check for impedance discontinuities on the trace by Time Domain
Reflectometry (TDR).
Revisit the board design, layout, and routing for any inconsistencies that can
cause impedance discontinuities.
Check whether the termination schemes on the Stratix IV GX device and on the
upstream system are matched. Altera recommends using OCT in the
Stratix IV GX device instead of external termination to improve signal
integrity.
Change the transmit output differential voltage to improve eye amplitude.
Some scopes, such as Agilent 86100C DCA, require pre-defined patterns
(for example, PRBS7 or PRBS23) to provide jitter components.
Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
Guidelines to Debug Transceiver-Based Designs
February 2011 Altera Corporation