EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 754

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

2–82
Document Revision History
Table 2–21. Document Revision History
Stratix IV Device Handbook Volume 2: Transceivers
February 2011
March 2010
November 2009
June 2009
March 2009
November 2008
May 2008
Date
Version
Table 2–21
3.0
1.0
3.2
3.1
2.2
2.1
20
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Minor updates.
Update to chapter.
Initial release.
Updated
Updated
Updated the
VCO Bypass Mode”
Applied new template.
Updated chapter title.
Applied new template.
Updated Table 2–4.
Updated Figure 2–7, Figure 2–8, Figure 2–16, and Figure 2–21.
Updated the “Transceiver Channel Datapath Clocking” and “Configuration Example 3:
Configuring Sixteen Channels Across Four Transceiver Blocks” sections.
Added a note to the “refclk0 and refclk1 Pins” section.
Changed “datapath clocks” to “datapath interface clocks”.
Minor text edits.
Added Figure 2–1, Figure 2–12,and Figure 2–13.
Added Table 2–1, Table 2–2, Table 2–8, and Table 2–2.
Updated Table 2–5 and Table 2–14.
Updated all graphics.
Updated all sections.
Added Stratix IV GT information.
Re-organized information.
Minor text edits.
Updated Figure 2–5 and Figure 2–7.
Updated the “Transceiver Data Rates Supported in Basic (PMA Direct) Mode”,
“FPGA Fabric PLLs-Transceiver PLLs Cascading in the 780-Pin Package”, “FPGA Fabric
PLLs-Transceiver PLLs Cascading in the 1152-Pin Package”, sections.
Removed Table 2-5, Table 2-6, Table 2-7
Removed Figure 2-17 and Figure 2-18.
Minor text edits.
lists the revision history for this chapter.
Table
Figure
“Configuration Example 4: Configuring Left and Right, Left, or Right PLL in
2–4.
2–7,
section.
Figure
2–18,
Figure
Changes
2–19,
Chapter 2: Transceiver Clocking in Stratix IV Devices
Figure
2–20.
February 2011 Altera Corporation
Document Revision History