EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 619

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–141. SONET/SDH OC-12 Datapath
Figure 1–142. SONET/SDH OC-48 Datapath
February 2011 Altera Corporation
tx_coreclk
rx_coreclk
tx_coreclk
rx_coreclk
FPGA
Fabric
Fabric
FPGA
FPGA Fabric-Transmitter
SONET/SDH OC-12 Datapath
Figure 1–141
mode.
SONET/SDH OC-48 Datapath
Figure 1–142
mode.
FPGA Fabric-Receiver
FPGA Fabric-Transmitter
FPGA Fabric-Receiver
Interface Clock
Interface Clock
Interface Clock
Interface Clock
shows the transceiver datapath when configured in SONET/SDH OC-12
shows the transceiver datapath when configured in SONET/SDH OC-48
tx_clkout
rx_clkout
Compensation
RX Phase
rx_clkout
Compensation
tx_clkout
FIFO
RX Phase
Compensation
FIFO
wrclk
TX Phase
Compensation
wrclk
FIFO
TX Phase
FIFO
rdclk
rdclk
Ordering
Byte
Transmitter Channel PCS
Low-Speed Parallel Clock
wrclk
Serializer
Transmitter Channel PCS
Receiver Channel PCS
Parallel Recovered Clock
Byte De-
serializer
Byte
/2
/2
Low-Speed Parallel Clock
Receiver Channel PCS
rdclk
Recovered Clock
Aligner
Word
Parallel
Aligner
Word
Stratix IV Device Handbook Volume 2: Transceivers
Serializer
Receiver Channel PMA
Transmitter Channel PMA
De-
Receiver Channel PMA
Transmitter Channel PMA
Serializer
Serializer
De-
Serializer
Divider
Local
Clock
Divider
Clock
Local
CDR
High-Speed
Serial Clock
CDR
High-Speed
Serial Clock
1–175