EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 363

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Passive Serial Configuration
Figure 10–11. Multi-Device PS Configuration Using an External Host
Note to
(1) Connect the resistor to a supply that provides an acceptable input signal for all Stratix IV devices in the chain. V
April 2011 Altera Corporation
meet the V
Figure
(MAX II Device or
Microprocessor)
External Host
ADDR
IH
10–11:
Memory
specification of the I/O on the device and the external host. Altera recommends powering up all configuration system I/Os with V
DATA0
Figure 10–11
circuit is similar to the PS configuration circuit for a single device, except the Stratix IV
devices are cascaded for multi-device configuration.
In multi-device PS configuration, the first device’s nCE pin is connected to GND, while
its nCEO pin is connected to nCE of the next device in the chain. The last device’s nCE
input comes from the previous device, while its nCEO pin is left floating. After the first
device completes configuration in a multi-device configuration chain, its nCEO pin
drives low to activate the second device’s nCE pin, which prompts the second device
to begin configuration. The second device in the chain begins configuration within
one clock cycle. Therefore, the transfer of data destinations is transparent to the
MAX II device. All other configuration pins (nCONFIG, nSTATUS, DCLK, DATA0, and
CONF_DONE) are connected to every device in the chain. Configuration signals can
require buffering to ensure signal integrity and prevent clock skew problems. Ensure
that the DCLK and DATA lines are buffered for every fourth device. Because all device
CONF_DONE pins are tied together, all devices initialize and enter user mode at the same
time.
Because all nSTATUS and CONF_DONE pins are tied together, if any device detects an
error, configuration stops for the entire chain and you must reconfigure the entire
chain. For example, if the first device flags an error on nSTATUS, it resets the chain by
pulling its nSTATUS pin low. This behavior is similar to a single device detecting an
error.
If the Auto-restart configuration after error option is turned on, the devices release
their nSTATUS pins after a reset time-out period (a maximum of 500 μs). After all
nSTATUS pins are released and pulled high, the MAX II device can try to reconfigure
the chain without needing to pulse nCONFIG low. If this option is turned off, the
MAX II device must generate a low-to-high transition (with a low pulse of at least
2 μs) on nCONFIG to restart the configuration process.
V
CCPGM (1)
10 k Ω
V
CCPGM (1)
shows how to configure multiple devices using a MAX II device. This
10 k Ω
GND
CONF_DONE
nSTATUS
nCE
DATA0
nCONFIG
DCLK
Stratix IV Device 1
MSEL2
MSEL1
MSEL0
nCEO
GND
V
CCPGM
CONF_DONE
nSTATUS
nCE
DATA0
nCONFIG
DCLK
Stratix IV Device 2
Stratix IV Device Handbook Volume 1
CCPGM
MSEL2
MSEL1
MSEL0
nCEO
must be high enough to
N.C.
GND
V
CCPGM
10–29
CCPGM
.