EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 586

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–142
Stratix IV Device Handbook Volume 2: Transceivers
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1
The rateswitch signal serves as the input signal to the PCIe rateswitch controller.
After seeing a transition on the rateswitch signal from the PHY-MAC layer, the PCIe
rateswitch controller performs the following operations:
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PCIe rateswitch controller location:
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When operating at the Gen 2 data rate, asserting the rx_digitalreset signal causes
the PCIe rateswitch circuitry to switch the transceiver to Gen 1 data rate.
When switching from Gen1 to Gen2 using the dynamic reconfiguration controller,
you must set the two ports of the dynamic reconfiguration controller, tx_preemp_0t
and tx_preemp_2t, to zero to meet the Gen2 de-emphasis specifications. When
switching from Gen2 to Gen1, if your system requires specific settings on
tx_preemp_01 and tx_preemp_2t, those values must be set at the respective two ports
of the dynamic reconfiguration controller to meet your system requirements.
When the PHY-MAC layer instructs a rateswitch between the Gen1 (2.5 Gbps) and
Gen2 (5 Gbps) signaling rates, both the transmitter high-speed serial and low-speed
parallel clock and the CDR recovered clock must switch to support the instructed data
rate. Stratix IV GX and GT transceivers have dedicated PCIe clock switch circuitry
located in the following blocks:
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Controls the PCIe clock switch circuitry to switch between Gen1 (2.5 Gbps) and
Gen2 (5 Gbps) signaling rate depending on the rateswitch signal level
Disables and resets the transmitter and receiver phase compensation FIFO
pointers until the PCIe clock switchover circuitry indicates successful rateswitch
completion
Communicates completion of rateswitch to the PCIe interface module, which in
turn communicates completion of the rateswitch to the PHY-MAC layer on the
pipephydonestatus signal
In PCIe ×1 mode, the PCIe rateswitch controller is located in the transceiver PCS of
each channel.
In PCIe ×4 mode, the PCIe rateswitch controller is located in CMU0_Channel within
the transceiver block.
In PCIe ×8 mode, the PCIe rateswitch controller is located in CMU0_Channel within
the master transceiver block.
Local clock divider in transmitter PMA of each transceiver channel
CMU0 clock divider in CMU0_Channel of each transceiver block
Receiver CDR in receiver PMA of each transceiver channel
PCIe Rateswitch Controller
PCIe Clock Switch Circuitry
Chapter 1: Transceiver Architecture in Stratix IV Devices
February 2011 Altera Corporation
Transceiver Block Architecture