EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 974

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

1–16
Table 1–2. MegaWizard Plug-In Manager Options (PLL/Ports Screen) (Part 3 of 3)
Stratix IV Device Handbook Volume 3
Create a rx_digitalreset
port for the digital portion of
the receiver.
Create a tx_digitalreset
port for the digital portion of
the transmitter.
Create a pll_locked port to
indicate PLL is in lock with
the reference input clock.
Create an
rx_locktorefclk port to
lock the RX CDR to the
reference clock.
Create an rx_locktodata
port to lock the RX CDR to
the received data.
Create an rx_pll_locked
port to indicate RX CDR is
locked to the input reference
clock.
Create an rx_freqlocked
port to indicate RX CDR is
locked to the received data.
Notes to
(1) LTR mode is lock-to-reference mode and LTD mode is lock-to-data mode.
(2) When rx_locktorefclk and rx_locktodata are both asserted high, rx_locktodata takes precedence over rx_locktorefclk, forcing
the CDR to lock to the received data. When both these signals are de-asserted, the LTR/LTD controller is configured in Automatic Lock mode.
ALTGX Setting
Table
1–2:
The receiver digital reset port is available in
Receiver only and Receiver and Transmitter
operation modes. This resets the PCS portion of the
receiver channel.
Altera recommends using this port to implement
the recommended reset sequence. The minimum
pulse width is two parallel clock cycles.
The transmitter digital reset port is available in
Transmitter only and Receiver and Transmitter
operation modes. This resets the PCS portion of the
transmitter channel.
Altera recommends using this port to implement
the recommended reset sequence. The minimum
pulse width is two parallel clock cycles.
Each CMU/ATX PLL has a dedicated pll_locked
signal that is fed to the FPGA fabric to indicate
when the PLL is locked to the input reference clock.
When this signal is asserted high, the LTR/LTD
controller forces the receiver CDR to lock to the
phase and frequency of the input reference clock.
When this signal is asserted high, the LTR/LTD
controller forces the receiver CDR to lock to the
received data. (1),
■
■
This signal is asserted high to indicate that the
receiver CDR has switched from LTR to LTD mode.
This signal has relevance only in Automatic Lock
mode and may be required to control the
transceiver resets, as described in the User Reset
and Power Down Signals section in the
Control and Power Down in Stratix IV Devices
chapter.
(1),
In LTR mode, this signal is asserted high to
indicate that the receiver CDR has locked to the
phase and frequency of the input reference
clock.
In LTD mode, this signal has no significance.
(2)
(1)
Description
(2)
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Reset
(1)
“User Reset and Power Down
Signals” section in the
and Power Down in Stratix IV Devices
chapter.
“User Reset and Power Down
Signals” section in the
and Power Down in Stratix IV Devices
chapter.
“Transceiver Reset Sequences”
section in the
Power Down in Stratix IV Devices
chapter.
“LTR/LTD Controller” section in the
Transceiver Architecture in Stratix IV
Devices
“LTR/LTD Controller” section in the
Transceiver Architecture in Stratix IV
Devices
“Lock-to-Reference (LTR) Mode”
section in the
in Stratix IV Devices
“LTR/LTD Controller” section in the
Transceiver Architecture in Stratix IV
Devices
chapter.
chapter.
chapter.
February 2011 Altera Corporation
Reference
Transceiver Architecture
Reset Control and
chapter.
Reset Control
Reset Control
Parameter Settings