EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 804

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

3–50
Document Revision History
Table 3–23. Document Revision History (Part 1 of 2)
Stratix IV Device Handbook Volume 2: Transceivers
February 2011
November 2009
June 2009
March 2009
Date
Version
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Table 3–23
4.0
4.1
3.1
3.0
If you enable the PCIe hard IP block using the PCI Express Compiler, the
Quartus II software has certain requirements for using the remaining transceiver
channels within the transceiver block in the other configurations. For more
information, refer to
Other Channels” on page
The Quartus II software supports two kinds of Basic (PMA Direct) configurations
(×1 and ×N).
If you use Basic (PMA Direct) ×1 configuration, you must use the CMU PLL
within the same transceiver block.
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Updated
Updated the
(VCCH)”,
“Combining Transceiver Instances Using PLL Cascade
Using the PCIe hard IP Block with Other
You Enable the Use Alternate CMU PLL
Channels at 9.9 Gbps to 11.3 Gbps”
Updated chapter title.
Applied new template.
Minor text edits.
Added “Sharing ATX PLLs” on page 3–9, “Combination Requirements When Channel
Reconfiguration is Enabled” on page 3–42, “Combining Transceiver Channels When the
Adaptive Equalization (AEQ) is Enabled” on page 3–47, and “Combination Requirements
for Stratix IV GT Devices” on page 3–49.
Added Figure 3–8, Figure 3–10, Figure 3–11, Figure 3–23, and Figure 3–24.
Updated all other sections.
Added Stratix IV GT information.
Updated graphics.
Minor text edits.
Updated Table 3–7.
Minor text edits.
Updated sections “Combining Channels Using the PCI Express Hard IP Block with Other
Channels” on page 3–17, “Convention Used” on page 3–21, “PMA Direct Mode
Restrictions” on page 3–22, “Multiple ‘PMA Direct x1’ Configuration Instances with One
Channel per Instance” on page 3–22, “Combining Multiple Instances of TX Only and RX
Only PMA-Direct x1 Configurations” on page 3–26, “Combining Transceiver Channels
with PMA Direct Configuration” on page 3–21.
Updated Table 3–7.
Updated Figure 3–19.
lists the revision history for this chapter.
Table
“Transceiver Analog Power
“Multiple Channels Sharing a CMU
3–15.
“Combining Channels Using the PCIe hard IP Block with
Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
3–24.
sections.
(VCCA_L/R)”,
Changes
Option”, and
Channels”,
PLL”,
“Calibration Clock and Power
“Combination Requirements When
“Placement Rules for Transceiver
“Transmitter Buffer Voltage
Clocks”,
February 2011 Altera Corporation
“Combining Channels
Document Revision History
Down”,