EP4SE530H40I3 Altera, EP4SE530H40I3 Datasheet - Page 1009

• Manufacturer Part Number: EP4SE530H40I3
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H40I3

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 976
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Protocol Settings
Table 1–16. MegaWizard Plug-In Manager Options (PCIe 1) (Part 1 of 2)
February 2011 Altera Corporation
Enable low latency synchronous
PCIe.
Enable run-length violation checking
with a run length of __.
Enable fast recovery mode.
Enable electrical idle inference
functionality.
Create an rx_syncstatus output
port for pattern detector and word
aligner.
ALTGX Setting
Table 1–16
Manager for your ALTGX custom megafunction variation.
lists the available options on the PCIe 1 screen of the MegaWizard Plug-In
This option puts the rate match FIFO into low latency
mode, which forces the system into a 0 ppm mode.
Ensure that there is a 0 ppm difference between the
upstream transmitter’s and the local receiver’s input
reference clocks.
This option creates the output signal rx_rlv.
Enabling this option also activates the run-length
violation circuit. If the number of continuous 1s and
0s exceeds the number that you set in this option,
the run-length violation circuit asserts the rx_rlv
signal. The rx_rlv signal is asynchronous to the
receiver data path.
For both 8-bit and 16-bit channel widths, the run
length limits are 5 to 160 in increments of five.
This option enables the CDR control block. When
this block is enabled, the rx_locktodata and
rx_locktorefclk signals are disabled.
Enable the electrical idle inference module by
selecting this option. In PCIe mode, the PCS has an
optional electrical idle inference module designed to
implement the electrical idle inference conditions
specified in PCIe base specification 2.0.
Enabling this option creates the
rx_elecidleinfersel[2:0] input signal. The
electrical idle Inference module infers electrical idle
depending on the logic level driven on the
rx_elecidleinfersel[2:0] input signal. For the
electrical idle Inference module to correctly infer an
electrical idle condition in each LTSSM sub-state,
you must drive the rx_elecidleinfersel[2:0]
signal appropriately.
The ALTGX MegaWizard Plug-In Manager
automatically configures the word aligner in
Automatic Synchronization State Machine mode for
PCIe mode. This is an output status signal that the
word aligner forwards to the FPGA fabric to indicate
that synchronization has been achieved. This signal
is synchronous with the parallel receiver data on the
rx_dataout port. The signal width is 1 and 2 bits
for a channel width of 8 bits and 16 bits,
respectively.
Description
Stratix IV Device Handbook Volume 3
“Rate Match (Clock Rate
Compensation) FIFO” section
in the
Architecture in Stratix IV
Devices
“Programmable Run Length
Violation Detection” section in
the
in Stratix IV Devices
“Fast Recovery Mode” section
in the
Architecture in Stratix IV
Devices
“Electrical Idle Inference”
section in the
Architecture in Stratix IV
Devices
Table 1-29 and “Automatic
Synchronization State
Machine Mode Word Aligner
with 10-bit PMA-PCS
Interface Mode” section in the
Transceiver Architecture in
Stratix IV Devices
Transceiver Architecture
Transceiver
Transceiver
chapter.
chapter.
chapter.
Reference
Transceiver
chapter.
chapter.
1–51