HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 9

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

• The typical product
• In order to understand the overall functions of the chip
• In order to understand the details of the CPU's functions
• In order to understand the details of a register when the user knows its name
Related Manuals:
SH7047 Group manuals:
Document Title
SH7047 Group Hardware Manual
SH-1, SH-2, SH-DSP Software Manual
The HD64F7047 is taken as the typical product for the descriptions in this manual.
Accordingly, when using an HD6437049, simply replace the HD64F7047 in those references
where no differences between products are pointed out with HD6437049. Where differences
are indicated, be aware that each specification apply to the products as indicated.
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
Read the SH-1, SH-2, SH-DSP Software Manual.
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bit names, and initial values of the registers are summarized in
Appendix A, Internal I/O Register.
Rules:
Register name:
Bit order:
The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com
The following notation is used for cases when the same or a
similar function, e.g. serial communication, is implemented
on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
The MSB (most significant bit) is on the left and the LSB
(least significant bit) is on the right.
Rev. 2.00, 09/04, page vii of xl
Document No.
This manual
REJ09B0171