HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 167

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Block Transfer Mode: Performs the transfer of one block for each one activation. Either the
transfer source or transfer destination is designated as the block area.
The block length is specified between 1 and 65536. When the transfer of one block ends, the
initial state of the block size counter and the address register specified as the block area is restored.
The other address register is then incremented, decremented, or left fixed.
From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a
CPU interrupt is requested.
Table 8.4
Register
DTMR
DTCRA
DTCRB
DTSAR
DTDAR
DTSAR
or
DTDAR
Block Transfer Mode Register Functions
Function
Operation mode
control
Transfer count
Block length
Transfer source
address
Transfer destination
address
Figure 8.8 Memory Mapping in Block Transfer Mode
First block
Nth block
•
•
•
Values Written Back upon a Transfer Information Write
DTMR
DTCRA – 1
(Not written back)
(DTS = 0) Increment/ decrement/ fixed
(DTS = 1) DTSAR initial value
(DTS = 0) DTDAR initial value
(DTS = 1) Increment/ decrement/ fixed
Transfer
Block area
Rev. 2.00, 09/04, page 125 of 720
DTDAR
or
DTSAR