HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 420

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.8.5
Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared
to 0.
12.8.6
1. When using an external clock source for the serial clock, update TDR with the DTC, and then
2. Before reading the receive data register (RDR) with the DTC, select the receive-data-full
12.8.7
1. Set TE = RE = 1 only when external clock SCK is 1.
2. Do not set TE = RE = 1 until at least four Pφ clocks after external clock SCK has changed
3. When receiving, RDRF is 1 when RE is cleared to 0 after 2.5–3.5 Pφ clocks from the rising
12.8.8
When receiving, RDRF is 1 when RE is cleared to 0 after 1.5 Pφ clocks from the rising edge of the
RxD D7 bit SCK output, but copying to RDR is not possible.
Rev. 2.00, 09/04, page 378 of 720
after the elapse of five peripheral clocks (Pφ) or more, input a transmit clock. If a transmit
clock is input in the first four Pφ clocks after TDR is written, an error may occur (figure
12.21).
(RXI) interrupt of the SCI as a start-up source.
from 0 to 1.
edge of the RxD D7 bit SCK input, but copying to RDR is not possible.
Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Constraints on DTC Use
Cautions on Clocked Synchronous External Clock Mode
Caution on Clocked Synchronous Internal Clock Mode
Figure 12.21 Example of Clocked Synchronous Transmission with DTC
Note: During external clock operation, an error may occur if t is 4 Pφ clocks or less.
SCK
TDRE
t
D0
D1
D2
D3
D4
D5
D6
D7