HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 550

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Writing Operation into Timer Period Data Register (TPDR) and Timer Dead Time Data
Register (TDDR) When MMT is Operating:
• Do not revise TPDR register when MMT is operating. Always use a buffer-write operation
• Do not revise TDDR register once an operation of MMT is invoked. When TDDR is revised, a
16.8
The port output enable (POE) circuit enables the MMT's output pins (POUA, POUB, POVA,
POVB, POWA, and POWB) to be placed in the high-impedance state by varying the input to pins
POE4 to POE6. An interrupt can also be requested at the same time.
In addition, the MMT's output pins will also enter the high-impedance state in standby mode or
when the oscillator halts.
16.8.1
The POE circuit has the following features:
• Falling edge, Pφ/8 × 16 times, Pφ/16 × 16 times, or Pφ/128 × 16 times low-level sampling can
• The MMT's output pins can be placed in the high-impedance state at the falling edge or low-
• An interrupt can be generated by input level sampling.
Rev. 2.00, 09/04, page 508 of 720
PreviousTGRU
through TPBR register.
wave may not be output for as much as 1 cycle (full count period of 16 bits in TDCNT),
because a value cannot be written into TDCNT, which is compared to a value set in TDDR.
be set for each of input pins POE4 to POE6.
level sampling of pins POE4 to POE6.
Figure 16.17 Writing into Timer General Registers (When One Cycle is Not Output)
TGRU
Port Output Enable (POE)
Features
2Td
Td
Count-up
PreviousTGRU
TGRU
2Td
Count down
Td