HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 454

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev. 2.00, 09/04, page 412 of 720
H'028
H'02A
H'030
H'032
H'038
H'03A
H'040
H'042
H'048
H'04A
H'050
H'052
H'058
H'05A
H'000
H'002
H'004
H'006
H'008
H'00A
H'00C
H'020
H'022
H'080
H'082
H'084
H'088
H'08C
H'08E
H'090
H'092
H'094
Bit 15
Transmit error counter
Unread message status register (UMSR1)
Unread message status register (UMSR0)
Mailbox interrupt mask register (MBIMR1)
Mailbox interrupt mask register (MBIMR0)
Timer compare match register 0 (TCMR0)
Timer compare match register 1 (TCMR1)
Transmit acknowledge register (TXACK1)
Transmit acknowledge register (TXACK0)
Bit timing configuration register 1 (BCR1)
Bit timing configuration register 0 (BCR0)
Transmit wait cancel register (TXCR1)
Transmit wait cancel register (TXCR0)
Abort acknowledge register (ABACK1)
Abort acknowledge register (ABACK0)
Remote request register (RFPR1)
Remote request register (RFPR0)
Timer counter register (TCNTR)
Transmit wait register (TXPR1)
Transmit wait register (TXPR0)
Receive wait register (RXPR1)
Receive wait register (RXPR0)
(TEC)
Input capture register 0 (ICR0)
Input capture register 1 (ICR1)
Master control register (MCR)
General status register (GSR)
Interrupt mask register (IMR)
Timer control register (TCR)
Local offset register (LOSR)
Timer status register (TSR)
Interrupt register (IRR)
Receive error counter
Figure 15.2 Register Configuration
(REC)
Bit 0
H'4A0
H'4C0
H'4E0
H'4F3
H'100
H'106
H'108
H'10A
H'10C
H'10E
H'110
H'120
H'140
H'160
H'2E0
H'2F3
H'300
(BaseID, ExtID, RTR, IDE, DLC, ATX, DART, MBC)
Mailbox 29 control/timestamp/data/LAFM
Mailbox 30 control/timestamp/data/LAFM
Mailbox 31 control/timestamp/data/LAFM
Mailbox 15 control/timestamp/data/LAFM
Mailbox 16 control/timestamp/data/LAFM
Mailbox 1 control/timestamp/data/LAFM
Mailbox 2 control/timestamp/data/LAFM
Mailbox 3 control/timestamp/data/LAFM
0
2
4
6
Mailbox 0 data (8 bytes)
Mailbox 0 timestamp
Mailbox 0 control
Mailbox 0 LAFM
1
3
5
7