HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 752

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev. 2.00, 09/04, page 710 of 720
Item
15.3.1 Master Control
Register (MCR)
15.3.2 General Status
Register (GSR)
15.3.5 Interrupt Request
Register (IRR)
15.3.8 Transmit Wait
Registers (TXPR1,
TXPR0)
15.3.9 Transmit Wait
Cancel Registers (TXCR1,
TXCR0)
15.3.10 Transmit
Acknowledge Registers
(TXACK1, TXACK0)
15.3.11 Abort
Acknowledge Registers
(ABACK1, ABACK0)
15.3.12 Receive Complete
Registers (RXPR1,
RXPR0)
15.3.13 Remote Request
Registers (RFPR1,
RFPR0)
15.3.14 Mailbox Interrupt
Mask Registers (MBIMR1,
MBIMR0)
15.3.15 Unread Message
Status Registers (UMSR1,
UMSR0)
15.3.16 Mailboxes (MB0
to MB31)
Page
416
417
418
419
426
430,
431
432,
433
434,
435
436,
437
438,
439
440,
441
442,
443
444,
445
447
Revisions (See Manual for Details)
Bit 5:
Amended.
Bit 1:
Amended.
Bit 0:
Note added.
Bit 3:
Clearing condition amended.
Bit 0:
Initial value 0 → 1
Description amended.
Description amended.
Description amended.
Description amended.
Description amended.
Description amended.
Description amended.
Description amended.
MBx[0] to
[1]
MBx[2] to
[3]
MBx[4] to
[5]
Note: Shaded bits are reserved. The write value should always be 0. The read value is not guaranteed.
Register
Name
H'100 +
N*32
H'102 +
N*32
H'104 +
N*32
Address
CCM
15
0
14
0
NMC
13
ATX
12
DART
11
10
STDID[10:0]
MBC[2:0]
9
EXTID[15:0]
Data Bus
8
7
0
TCT
6
5
0
4
0
3