HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 740

IC H8 MCU FLASH 256K 100TQFP

HD64F7047F50V

Manufacturer Part Number
HD64F7047F50V
Description
IC H8 MCU FLASH 256K 100TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheets

Specifications of HD64F7047F50V

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Package
100PQFP
Family Name
SuperH
Maximum Speed
50 MHz
Operating Supply Voltage
5 V
Data Bus Width
32 Bit
Number Of Programmable I/os
53
Interface Type
CAN/SCI
On-chip Adc
16-chx10-bit
Number Of Timers
7
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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The initial values differ in each MCU operating mode. For details, refer to section 17, Pin
Function Controller (PFC).
Table B.1
Rev. 2.00, 09/04, page 698 of 720
Type
Clock
System
Control
Operation
Mode
Control
Interrupt
Address
Bus
Data Bus
Bus
Control
HCAN2
MTU
Pin Function
Pin Name
CK
XTAL
EXTAL
PLLCAP
RES
MRES
WDTOVF
BREQ
BACK
MD0 to MD3
DBGMD
FWP
NMI
IRQ0 to IRQ3
IRQOUT
A0 to A17
D0 to D7
WAIT
CS0
RD
WRL
HTxD1
HRxD1
TCLKA to
TCLKD
TIOC0A to
TIOC0D
TIOC1A,
TIOC1B
TIOC2A,
TIOC2B
TIOC3A,
TIOC3C
TIOC3B,
TIOC3D
TIOC4A to
TIOC4D
Pin States (1)
ROM
Enabled
O
I
I
I
Z
O*
Z
Z
I
I
Z
Z
O
Z
Z
H
H
H
Z
Z
Z
O
I
I
Z
Z
3
ROM
Disabled
Z
Z
Z
Z
Power-On
Appendix B Pin States
Reset State
Single-
Chip
Z
Manual
O
O
I
I
I
I
O
I
O
I
I
I
I
I
O
O
I/O
I
O
O
O
O
I
I
I/O
I/O
Hardware
Standby
Z
L
Z
I
I
Z
O
Z
Z
I
I
I
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Power-Down State
Z
Software
Standby
O
L
I
I
I
Z*
O
Z
Z
I
I
I
I
Z*
K*
Z
Z
O
O
O
O*
Z
Z
K*
Z*
2
4
2
1
1
1
Sleep
O
O
I
I
I
I
O
I
O
I
I
I
I
I
O
O
I/O
I
O
O
O
O
I
I
I/O
I/O
Pin State
Bus
Release
State
O
O
I
I
I
I
O
I
L
I
I
I
I
I
O
Z
Z
Z
Z
Z
Z
O
I
I
I/O
I/O
Software
Standby in
Bus Right
Release
State
O
L
I
I
I
Z*
O
I
L
I
I
I
Z*
K*
Z
Z
Z
Z
Z
Z
O*
Z
Z
K*
Z*
I
2
4
1
1
2
1

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