HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 410

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.6
Figure 12.14 shows the general format for clocked synchronous communication. In clocked
synchronous mode, data is transmitted or received in synchronization with clock pulses. Data is
transferred in 8-bit units. In clocked synchronous serial communication, data on the transmission
line is output from one falling edge of the serial clock to the next. In clocked synchronous mode,
the SCI receives data in synchronization with the rising edge of the serial clock. After 8-bit data is
output, the transmission line holds the MSB state. In clocked synchronous mode, no parity or
multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units,
enabling full-duplex communication by use of a common clock. Both the transmitter and the
receiver also have a double-buffered structure, so that data can be read or written during
transmission or reception, enabling continuous data transfer.
12.6.1
Either an internal clock generated by the on-chip baud rate generator or an external
synchronization clock input at the SCK pin can be selected, according to the setting of CKE1 and
CKE0 bits in SCR. When the SCI is operated on an internal clock, the serial clock is output from
the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no
transfer is performed, the clock is fixed high. Only in reception, the serial clock is continued
generating until an overrun error is occurred or the RE bit is cleared to 0. To execute reception in
one-character units, select an external clock as a clock source.
12.6.2
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then
initialize the SCI as described in a sample flowchart in figure 12.15. When the operating mode,
transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the
change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1.
Note that clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER flags, or the
contents of RDR.
Rev. 2.00, 09/04, page 368 of 720
Figure 12.14 Data Format in Clocked Synchronous Communication (For LSB-First)
Synchronization
clock
Serial data
Note: * High except in continuous transfer
Operation in Clocked Synchronous Mode
Clock
SCI initialization (Clocked Synchronous mode)
Don’t care
*
LSB
Bit 0
One unit of transfer data (character or frame)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
MSB
Bit 7
Don’t care
*