HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 377

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.3.6
SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt
requests, and selection of the transfer clock source. For details on interrupt requests, refer to
section 12.7, SCI Interrupts.
Bit
1
0
Bit
7
6
5
4
Bit Name
CKS1
CKS0
Bit Name
TIE
RIE
TE
RE
Serial Control Register (SCR)
Initial
Value
0
0
Initial
Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Clock Select 1 and 0
These bits select the clock source for the baud rate
generator.
00: Pφ clock (n = 0)
01: Pφ/8 clock (n = 1)
10:Pφ/32 clock (n = 2)
11:Pφ/128 clock (n = 3)
For the relation between the bit rate register setting
and the baud rate, see section 12.3.9, Bit Rate
Register (BRR). n is the decimal display of the value
of n in BRR (see section 12.3.9, Bit Rate Register
(BRR)).
Description
Transmit Interrupt Enable
When this bit is set to 1, TXI interrupt request is
enabled.
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
Transmit Enable
When this bit is set to 1, transmission is enabled.
Receive Enable
When this bit is set to 1, reception is enabled.
Rev. 2.00, 09/04, page 335 of 720