HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 463

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
10
9
8
7, 6
5
4
3 to 1
0
11
Bit Name
TSEG2_2
TSEG2_1
TSEG2_0
—
SJW1
SJW0
—
BSP
—
Initial
Value
0
0
0
0
All 0
0
0
All 0
0
R/W
R/W
R/W
R/W
R
R/W
R/W
R
R/W
R
Description
Time Segment 2 (TSEG2)
Set the TSEG2 (PHSEG2) size as a value from 2 to 8
time quanta.
000: Setting prohibited
001: 2 time quanta
010: 3 time quanta
011: 4 time quanta
100: 5 time quanta
101: 6 time quanta
110: 7 time quanta
111: 8 time quanta
Reserved
These bits are always read as 0. The write value should
always be 0.
Re-Synchronization Jump Width (SJW)
Set the maximum bit synchronization width.
00: 1 time quantum
01: 2 time quanta
10: 3 time quanta
11: 4 time quanta
Reserved
These bits are always read as 0. The write value should
always be 0.
Bit Sample Point (BSP)
Sets the point at which data is sampled.
0: Bit sampling at one point (end of TSEG1)
1: Bit sampling at three points (end of TSEG1, and 1 time
Note: When this bit is set to 1, the baud rate prescaler
Reserved
This bit is always read as 0. The write value should
always be 0.
quantum before and after)
value which is set in BRP7 to BRP0 bits in BCR0
should be set below 5 system clocks.
Rev. 2.00, 09/04, page 421 of 720