HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 105

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.3
5.3.1
Address errors occur when instructions are fetched or data is read or written, as shown in table 5.6.
Table 5.6
Note:
Type
Instruction
fetch
Data
read/write
*
Bus Cycle
Address Errors
The Cause of Address Error Exception
See section 9, Bus State Controller (BSC) for more information on the on-chip
peripheral module space.
Bus Cycles and Address Errors
Bus Master
CPU
CPU, DTC,
or AUD
Bus Cycle Description
Instruction fetched from even address
Instruction fetched from odd address
Instruction fetched from other than on-chip
peripheral module space*
Instruction fetched from on-chip peripheral
module space*
Instruction fetched from external memory
space when in single chip mode
Word data accessed from even address
Word data accessed from odd address
Longword data accessed from a longword
boundary
Longword data accessed from other than a
long-word boundary
Byte or word data accessed in on-chip
peripheral module space*
Longword data accessed in 16-bit on-chip
peripheral module space*
Longword data accessed in 8-bit on-chip
peripheral module space*
External memory space accessed when in
single chip mode
Rev. 2.00, 09/04, page 63 of 720
Address Errors
None (normal)
Address error occurs
None (normal)
Address error occurs
Address error occurs
None (normal)
Address error occurs
None (normal)
Address error occurs
None (normal)
None (normal)
Address error occurs
Address error occurs