HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 82

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

System Control Instructions:
Rev. 2.00, 09/04, page 40 of 720
Instruction
CLRT
CLRMAC
LDC
LDC
LDC
LDC.L @Rm+,SR
LDC.L @Rm+,GBR
LDC.L @Rm+,VBR
LDS
LDS
LDS
LDS.L @Rm+,MACH
LDS.L @Rm+,MACL
LDS.L @Rm+,PR
NOP
RTE
SETT
SLEEP
STC
STC
STC
STC.L SR,@–Rn
STC.L GBR,@–Rn
STC.L VBR,@–Rn
STS
STS
STS
STS.L MACH,@–Rn
STS.L MACL,@–Rn
Rm,SR
Rm,GBR
Rm,VBR
Rm,MACH
Rm,MACL
Rm,PR
SR,Rn
GBR,Rn
VBR,Rn
MACH,Rn
MACL,Rn
PR,Rn
Instruction Code
0000000000001000
0000000000101000
0100mmmm00001110
0100mmmm00011110
0100mmmm00101110
0100mmmm00000111
0100mmmm00010111
0100mmmm00100111
0100mmmm00001010
0100mmmm00011010
0100mmmm00101010
0100mmmm00000110
0100mmmm00010110
0100mmmm00100110
0000000000001001
0000000000101011
0000000000011000
0000000000011011
0000nnnn00000010
0000nnnn00010010
0000nnnn00100010
0100nnnn00000011
0100nnnn00010011
0100nnnn00100011
0000nnnn00001010
0000nnnn00011010
0000nnnn00101010
0100nnnn00000010
0100nnnn00010010
Operation
0 → T
0 → MACH, MACL
Rm → SR
Rm → GBR
Rm → VBR
(Rm) → SR, Rm + 4 → Rm
(Rm) → GBR, Rm + 4 → Rm
(Rm) → VBR, Rm + 4 → Rm
Rm → MACH
Rm → MACL
Rm → PR
(Rm) → MACH, Rm + 4 → Rm 1
(Rm) → MACL, Rm + 4 → Rm 1
(Rm) → PR, Rm + 4 → Rm
No operation
Delayed branch, stack area
→ PC/SR
1 → T
Sleep
SR → Rn
GBR → Rn
VBR → Rn
Rn – 4 → Rn, SR → (Rn)
Rn – 4 → Rn, GBR → (Rn)
Rn – 4 → Rn, VBR → (Rn)
MACH → Rn
MACL → Rn
PR → Rn
Rn – 4 → Rn, MACH → (Rn)
Rn – 4 → Rn, MACL → (Rn)
Execution
States
1
1
1
1
1
3
3
3
1
1
1
1
1
4
1
3*
1
1
1
2
2
2
1
1
1
1
1
T Bit
0

LSB


LSB










1











