HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 522

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.8.3
The bus operation interrupt flag (IRR12) in the interrupt register (IRR) is set by CAN bus
operation in HCAN2 sleep mode. Therefore, this flag is not used by the HCAN2 to indicate sleep
mode release. Note that the reset status bit (GSR3) in the general status register (GSR) is set in
HCAN2 sleep mode.
15.8.4
When the mailbox interrupt mask register (MBIMR) is set, the interrupt register (IRR8, IRR2, or
IRR1) is not set by reception completion, transmission completion, or transmission cancellation
for the set mailboxes.
15.8.5
In the case of error active and error passive, REC and TEC normally count up and down. In the
bus-off state, 11-bit recessive sequences are counted (REC + 1) using REC. If REC reaches 96
during the count, IRR4 and GSR1 are set, and if REC reaches 128, IRR7 is set.
15.8.6
HCAN2 registers except some registers can be accessed only in words. The registers for
mailboxes, MBx[4], MBx[5], and MBx[7] to [14], can be accessed in both bytes and words. The
registers should not be accessed in longwords.
15.8.7
All HCAN2 registers are initialized in hardware standby mode and software standby mode.
15.8.8
Setting the contents of TXCR at the SOF or in the intermission state causes a message
transmission and TXACK to be set at the completion of the transmission. However, clearing the
contents of TXCR and TXPR and setting the contents of ABACK are automatically performed.
Despite that both transmission-cancellation and transmission-completion flags are set, incorrect
data will not transmitted.
Rev. 2.00, 09/04, page 480 of 720
HCAN2 Sleep Mode
Interrupts
Error Counters
Register Access
Register in Standby Modes
Transmission Cancellation during SOF or Intermission