HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 753

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Item
15.3.16 Mailboxes (MB0
to MB31)
15.3.18 Timer Control
Register (TCR)
15.4.1 Hardware and
Software Resets
•
15.4.2 Initialization after
Hardware Reset
Figure 15.5 Hardware
Reset Flowchart
Figure 15.6 Software
Reset Flowchart
Table 15.5 Setting Range
for TSEG1 and TSEG2 in
BCR
15.4.2 Initialization after
Hardware Reset
Mailbox Transmit/Receive
Settings:
Figure 15.8 Transmission
Flowchart by Event
Trigger
Software Reset
Page
448,
450
449
452
453
455 to
457
460
460
461
462
464
465
466
Revisions (See Manual for Details)
Bits 15, 11, and 6 in the MBx[4] and MBx[5] registers:
Note added.
Bits 13 in the MBx[4] and MBx[5] registers:
Description added.
Bits 15 to 0 in the MBx[6] register:
Description amended.
Note amended.
Note:
Description amended.
Description amended.
These initial settings must be made while the HCAN2 is in
configuration mode. Deleted Configuration mode is a state in
which the GSR3 bit in GSR is set by a reset.
Amended.
Amended.
Note added.
Note added.
*
When MBC = B'001, B'010, B'100, and B'101,
these registers become a local acceptance filter
mask (LAFM) field.
Interrupt to CPU (SLE1)
Clear TXACK
Clear IRR8
IMR8=1?
No
Rev. 2.00, 09/04, page 711 of 720
Yes