HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 747

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Item
Precaution on Handling
HCAN2
1.4 Pin Functions
Figure 3.2 The Address
Map for the Operating
Modes of SH7049 Mask
ROM Version
4.3.1 Note on Crystal
Resonator
Table 5.3 Exception
Processing Vector Table
Table 9.2 Address Map
Table 10.10 TIORH_0
(channel 0) to Table 10.25
TIORL_4 (channel 4)
Table 10.24 TIORL_4
(channel 4)
Main Revisions and Additions in this Edition
Page
All
10
49
55
60
137
164 to
179
178
Revisions (See Manual for Details)
SH7047 Series → SH7047 group
Added.
As the resonator circuit constants will depend on the resonator
and the floating capacitance of the mounting circuit, the
component value should be determined in consultation with the
resonator manufacturer.
• On-chip ROM disabled mode
Output hold* → Output hold
Notes: 2. When the BFB bit in TMDR_4 is set to 1 and TGRC_4 is used as a
Exception Sources
On-chip peripheral module
Address
H'0004 0000 to H'FFFF 7FFF
Type
User break
controller (UBC)
(flash memory
version only)
H'00000000
H'FFFFDFFF
H'FFFFE000
H'FFFFFFFF
buffer register, this setting is invalid and input capture/output compare
is not generated.
Reserved area
On-chip RAM
CS0 area
Mode 0
Symbol
UBCTRG
*
H'00000000
H'FFFFDFFF
H'FFFFE000
H'FFFFFFFF
2
Vector Numbers Vector Table Address Offset
72
255
:
ROM: 128 kbytes, RAM: 8 kbytes
Function
UBC condition match trigger output pin.
Rev. 2.00, 09/04, page 705 of 720
Reserved area
On-chip ROM
Space*
Reserved
On-chip RAM
Mode 2
H'00000120 to H'00000123
H'000003FC to H'000003FF
H'FFFFE000
H'FFFFFFFF
H'00000000
H'0001FFFF
Memory
Reserved
On-chip ROM
On-chip RAM
Mode 3
: