HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 366

IC H8 MCU FLASH 256K 100TQFP

HD64F7047F50V

Manufacturer Part Number
HD64F7047F50V
Description
IC H8 MCU FLASH 256K 100TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheets

Specifications of HD64F7047F50V

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Package
100PQFP
Family Name
SuperH
Maximum Speed
50 MHz
Operating Supply Voltage
5 V
Data Bus Width
32 Bit
Number Of Programmable I/os
53
Interface Type
CAN/SCI
On-chip Adc
16-chx10-bit
Number Of Timers
7
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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11.4.3
The watchdog timer has a special function to clear software standby mode with an NMI interrupt
or IRQ0 to IRQ3 interrupts. When using software standby mode, set the WDT as described below.
Before Transition to Software Standby Mode: The TME bit in TCSR must be cleared to 0 to
stop the watchdog timer counter before entering software standby mode. The chip cannot enter
software standby mode while the TME bit is set to 1. Set bits CKS2 to CKS0 in TCSR so that the
counter overflow interval is equal to or longer than the oscillation settling time. See section 25.3,
AC Characteristics, for the oscillation settling time.
Recovery from Software Standby Mode: When an NMI signal or IRQ0 to IRQ3 signals are
received in software standby mode, the clock oscillator starts running and TCNT starts
incrementing at the rate selected by bits CKS2 to CKS0 before software standby mode was
entered. When TCNT overflows (changes from H'FF to H'00), the clock is presumed to be stable
and usable; clock signals are supplied to the entire chip and software standby mode ends.
For details on software standby mode, see section 24, Power-Down Modes.
11.4.4
In interval timer mode, when TCNT overflows, the OVF bit of TCSR is set to 1 and an interval
timer interrupt (ITI) is simultaneously requested. Figure 11.4 shows this timing.
Rev. 2.00, 09/04, page 324 of 720
Clearing Software Standby Mode
Timing of Setting the Overflow Flag (OVF)
φ
TCNT
Overflow signal
(internal signal)
OVF
Figure 11.4 Timing of Setting OVF
H'FF
H'00

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