HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 170

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.3.6
Table 8.5 shows the execution state for one DTC data transfer. Furthermore, Table 8.6 shows the
state counts needed for execution state.
Table 8.5
N: block size (default set values of DTCRB)
Table 8.6
Notes: 1. Two state access module: port, INT, CMT, SCI, etc.
The execution state count is calculated using the following formula. Σ indicates the number of
transfers by one activating source (count + 1 when CHNE bit is set to 1).
Rev. 2.00, 09/04, page 128 of 720
Mode
Normal
Repeat
Block transfer
Access Objective
Bus width
Access state
Execution
state
2. Three state access module: WDT, UBC, etc.
Execution state count = I · S
DTC Execution State Counts
Vector read
Register information
read/write
Byte data read
Word data read
Long word data read
Byte data write
Word data write
Longword data write
Internal operation
Execution State of DTC
State Counts Needed for Execution State
Vector Read
I
1
1
1
Register
Information
Read/Write
J
7
7
7
I
+ Σ (J · S
S
S
S
S
S
S
S
S
S
I
J
K
K
K
L
L
L
M
On-chip
RAM
32
1

1
1
1
1
1
1
1
1
J
+ K · S
Data Read
K
1
1
N
K
+ L · S
On-chip
ROM
32
1
1
1
1
1
1
1
1
1
1
L
) + M · S
Data Write
L
1
1
N
Internal I/O
Register
32
2*


2
2
4
2
2
4
1
1
M
32
3*


3
3
6
3
3
6
1
2
Internal
Operation
M
1
1
1
External
Device
8
2
4
8
2
4
8
2
4
8
1