HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 629

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

22.4
22.4.1
When an H-UDI interrupt instruction is transferred to SDIR via TDI, an interrupt is generated.
Data transfer can be controlled by means of the H-UDI interrupt service routine. Transfer can be
performed by means of SDDR.
Control of data input/output between an external device and the H-UDI is performed by
monitoring the SDTRF bit in SDSR externally and internally. Internal SDTRF bit monitoring is
carried out by having SDSR read by the CPU.
The H-UDI interrupt and serial transfer procedure is as follows.
1. An instruction is input to SDIR by serial transfer, and an H-UDI interrupt request is generated.
2. After the H-UDI interrupt request is issued, the SDTRF bit in SDSR is monitored externally.
3. On completion of the serial transfer to SDDR, the SDTRF bit is cleared to 0, and SDDR can be
4. Serial data transfer between an external device and the H-UDI can be carried out by constantly
Figures 22.2, 22.3, and 22.4 show the timing of data transfer between an external device and the
H-UDI.
After output of SDTRF = 1 from TDO is observed, serial data is transferred to SDDR.
accessed by the CPU. After SDDR has been accessed, SDDR serial transfer is enabled by
setting the SDTRF bit in SDSR to 1.
monitoring the SDTRF bit in SDSR externally and internally.
Operation
H-UDI Interrupt
Rev. 2.00, 09/04, page 587 of 720