HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 490

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev. 2.00, 09/04, page 448 of 720
Register
Name
MBx[0],
MBx[1]
MBx[2],
MBx[3]
MBx[4],
MBx[5]
Bit
15
14 to 4
3
2
1, 0
15 to 0
15
14
Bit Name
—
STDID[10:0] R/W
RTR
IDE
EXTID[17:16] R/W
EXTID[15:0]
CCM

R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
The initial values of these bits are undefined; they
must be initialized (by writing 0).
Set the identifier (standard) of data frames and
remote frames.
Remote Transmission Request
Used to distinguish between data frames and remote
frames.
0: Data frame
1: Remote frame
In a case where the MBC2 to MBC0 bits in MBx[4] =
001 and ATX bit in MBx[4] = 1 (in a case where
automatic transmission function of data frame is
used), this bit will not be overwritten to 1 after
receiving remote frame.
Identifier Extension
Used to distinguish between the standard format and
extended format.
0: Standard format
1: Extended format
Set the identifier (extended) of data frames and
remote frames.
CAN-ID Compare Match
When this bit is set, the corresponding mailbox
receiving a message can trigger two actions. If the
TCR9 bit is set to 1, the reception of the message
will automatically clear the TCR14 bit (causing ICR0
to freeze). If the TCR10 bit is set to 1, the reception
of the message will automatically clear the timer
counter register (TCNTR) and set it to the local offset
register (LOSR) value.
Note:
The initial values of these bits are undefined; they
must be initialized (by writing 0).
This function is not supported in this LSI.
Therefore, the write value should always be
0. The read value is not guaranteed.