HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 755

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Item
15.7 CAN Bus Interface
Figure 15.16 High-Speed
Interface Using HA13721
15.8 Usage Notes
16.3.2 Timer Control
Register (TCNR)
Figure 16.5 Example of
PWM Waveform
Generation
16.7.2 Notes for MMT
Operation
16.8.5 Usage Notes
17.2 Precautions for Use
19.1 Features
Figure 19.10 Erase/Erase-
Verify Flowchart
19.13 Notes on Flash
Memory Programming
and Erasing
Page
479
479
479 to
482
488
498
507,
508
513
536
549
568
571
Revisions (See Manual for Details)
A bus transceiver IC is necessary to connect this LSI to a CAN
bus. A Renesas HA13721 transceiver IC and its compatible
products are recommended.
Amended.
Amended.
The timer control register (TCNR) controls the enabling or
disabling of interrupt requests, selects the enabling or disabling
of register access, and selects counter operation or halting.
Amended.
Descriptions added.
1. To set the POE pin as a level-detective pin, a high level
2. To clear bits POE4F, POE5F, and POE6F to 0, read the
Description 3 to 5 added.
•
Added.
ICSR2 register. Clear bits, which are read as 1, to 0, and
write 1 to the other bits in the register.
signal must be firstly input to the POE pin.
Reprogramming capability
 For details, see section 25, Electrical Characteristics.
Wait (t
SWE bit ← 1
Rev. 2.00, 09/04, page 713 of 720
Erase start
n ← 1
SSWE
) µs
* 1