HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 502

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.4
15.4.1
The HCAN2 can be reset by hardware or software.
• Hardware Reset
• Software Reset
15.4.2
After a hardware reset, the following initialization processing should be carried out:
1. Clearing of IRR0 bit in the interrupt request register (IRR)
2. Port settings of HCAN2 pins
3. Bit rate setting
4. Mailbox (RAM) initialization
5. Mailbox transmit/receive settings
6. Message transmission method setting
These initial settings must be made while the HCAN2 is in configuration mode. Configuration
mode is a state in which the GSR3 bit in GSR is set by a reset. If the MCR0 bit in MCR is cleared
to 0, for a while, configuration mode is aborted shortly after the HCAN2 automatically clears the
GSR3 bit in GSR. There is a delay between clearing the MCR0 bit and clearing the GSR3 bit
because the HCAN2 needs time to be internally reset. After the HCAN2 exits configuration mode,
the power-up sequence begins, and communication with the CAN bus is possible as soon as 11
consecutive recessive bits have been detected.
Rev. 2.00, 09/04, page 460 of 720
At power-on reset, manual reset, or in hardware or software standby mode, the HCAN2 is
initialized by automatically setting the reset request bit (MCR0) in MCR and the reset status
bit (GSR3) in GSR. At the same time, all internal registers, except for mailboxes (MB0 to
MB31), are initialized by a hardware reset. Figure 15.5 shows a flowchart in a hardware reset.
In the normal operating state, the HCAN2 can be reset by setting the reset request bit (MCR0)
in MCR (software reset). In a software reset, if the CAN controller is performing a
communication operation (transmission or reception), the HCAN2 enters the initialization state
after message transmission or reception has completed. A software reset is enabled after the
HCAN2 has entered from the bus off state to the error active state. The reset status bit (GSR3)
in GSR is set during initialization. In this initialization, error counters (TEC and REC) are
initialized, but other registers and RAM are not initialized.
Figure 15.6 shows a flowchart in a software reset.
Operation
Hardware and Software Resets
Initialization after Hardware Reset