HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 117
![IC H8 MCU FLASH 256K 100TQFP](/photos/12/21/122166/qfp100-g1_pkg_sml.jpg)
HD64F7047F50V
Manufacturer Part Number
HD64F7047F50V
Description
IC H8 MCU FLASH 256K 100TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Specifications of HD64F7047F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Package
100PQFP
Family Name
SuperH
Maximum Speed
50 MHz
Operating Supply Voltage
5 V
Data Bus Width
32 Bit
Number Of Programmable I/os
53
Interface Type
CAN/SCI
On-chip Adc
16-chx10-bit
Number Of Timers
7
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Price
Company:
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HD64F7047F50V
Manufacturer:
PANJIT
Quantity:
30 000
Company:
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HD64F7047F50V
Manufacturer:
RENESAS
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386
Company:
Part Number:
HD64F7047F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F7047F50V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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6.2
Table 6.1 shows the INTC pin configuration.
Table 6.1
6.3
The interrupt controller has the following registers. For details on register addresses and register
states during each processing, refer to appendix A, Internal I/O Register.
• Interrupt control register 1 (ICR1)
• Interrupt control register 2 (ICR2)
• IRQ status register (ISR)
• Interrupt priority register A (IPRA)
• Interrupt priority register D (IPRD)
• Interrupt priority register E (IPRE)
• Interrupt priority register F (IPRF)
• Interrupt priority register G (IPRG)
• Interrupt priority register H (IPRH)
• Interrupt priority register I (IPRI)
• Interrupt priority register K (IPRK)
Name
Non-maskable interrupt input pin
Interrupt request input pins
Interrupt request output pin
Input/Output Pins
Register Descriptions
Pin Configuration
IRQ0 to IRQ3
IRQOUT
Abbreviation
NMI
I/O
I
I
O
Function
Input of non-maskable interrupt
request signal
Input of maskable interrupt request
signals
Output of notification signal when an
interrupt has occurred
Rev. 2.00, 09/04, page 75 of 720
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