HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 469

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.3.6
IMR is a 16-bit register that enables interrupt requests caused by IRR interrupt flags.
Bit
15
14
13
12
11, 10
9
8
7
6
5
4
Bit Name
IMR15
IMR14
IMR13
IMR12

IMR9
IMR8
IMR7
IMR6
IMR5
IMR4
Interrupt Mask Register (IMR)
Initial
Value
1
1
1
1
All 1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Description
Timer Compare Match Interrupt 1 Mask
When this bit is cleared to 0, OVR1 (interrupt request by
IRR15) is enabled. When set to 1, OVR1 is masked.
Timer Compare Match Interrupt 0 Mask
When this bit is cleared to 0, OVR1 (interrupt request by
IRR14) is enabled. When set to 1, OVR1 is masked.
Timer Overflow Interrupt Mask
When this bit is cleared to 0, OVR1 (interrupt request by
IRR13) is enabled. When set to 1, OVR1 is masked.
Bus Operation Interrupt Mask
When this bit is cleared to 0, OVR1 (interrupt request by
IRR12) is enabled. When set to 1, OVR1 is masked.
Reserved
These bits are always read as 1. The write value should
always be 1.
Unread Interrupt Mask
When this bit is cleared to 0, OVR1 (interrupt request by
IRR9) is enabled. When set to 1, OVR1 is masked.
Mailbox Empty Interrupt Mask
When this bit is cleared to 0, SLE1 (interrupt request by
IRR8) is enabled. When set to 1, SLE1 is masked.
Overload Frame Interrupt Mask
When this bit is cleared to 0, OVR1 (interrupt request by
IRR7) is enabled. When set to 1, OVR1 is masked.
Bus Off/Bus Off Recovery Interrupt Mask
When this bit is cleared to 0, ERS1 (interrupt request by
IRR6) is enabled. When set to 1, ERS1 is masked.
Error Passive Interrupt Mask
When this bit is cleared to 0, ERS1 (interrupt request by
IRR5) is enabled. When set to 1, ERS1 is masked.
Receive Error Warning Interrupt Mask
When this bit is cleared to 0, ERS1 (interrupt request by
IRR4) is enabled. When set to 1, ERS1 is masked.
Rev. 2.00, 09/04, page 427 of 720