HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 352

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev. 2.00, 09/04, page 310 of 720
Bit
11 to 9 
8
7
6
5
4
3
2
Bit Name
POE3M1
POE3M0
POE2M1
POE2M0
POE1M1
POE1M0
PIE
Initial
value
All 0
0
0
0
0
0
0
0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. These bits should always
be written with 0
Port Interrupt Enable
This bit enables/disables interrupt requests when any of
the POE0F to POE3F bits of the ICSR1 are set to 1
0: Interrupt requests disabled
1: Interrupt requests enabled
POE3 mode 1, 0
These bits select the input mode of the POE3 pin
00: Accept request on falling edge of POE3 input
01: Accept request when POE3 input has been sampled
10: Accept request when POE3 input has been sampled
11: Accept request when POE3 input has been sampled
POE2 mode 1, 0
These bits select the input mode of the POE2 pin
00: Accept request on falling edge of POE2 input
01: Accept request when POE2 input has been sampled
10: Accept request when POE2 input has been sampled
11: Accept request when POE2 input has been sampled
POE1 mode 1, 0
These bits select the input mode of the POE1 pin
00: Accept request on falling edge of POE1 input
01: Accept request when POE1 input has been sampled
10: Accept request when POE1 input has been sampled
11: Accept request when POE1 input has been sampled
for 16 Pφ/8 clock pulses, and all are low level.
for 16 Pφ/16 clock pulses, and all are low level.
for 16 Pφ/128 clock pulses, and all are low level.
for 16 Pφ/8 clock pulses, and all are low level.
for 16 Pφ/16 clock pulses, and all are low level.
for 16 Pφ/128 clock pulses, and all are low level.
for 16 Pφ/8 clock pulses, and all are low level.
for 16 Pφ/16 clock pulses, and all are low level.
for 16 Pφ/128 clock pulses, and all are low level.