HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 574

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Notes: 1. F-ZTAT only. Setting prohibited for the mask version.
17.1.7
The port E I/O registers L and H (PEIORL and PEIORH) are 16-bit readable/writable registers
that are used to set the pins on port E as inputs or outputs. Bits PE21IOR to PE0IOR correspond to
pins PE21 to PE0 (names of multiplexed pins are here given as port names and pin numbers
alone). PEIORL is enabled when the port E pins are functioning as general-purpose inputs/outputs
(PE15 to PD0), TIOC pins are functioning as inputs/outputs of MTU, and SCK2 and SCK3 pins
are functioning as inputs/outputs of SCI. In other states, PEIORL is disabled. PEIORH is enabled
when the port E pins are functioning as general-purpose inputs/outputs (PE21 to PE16) and SCK4
pins are functioning as inputs/outputs of SCI. In other states, PEIORH is disabled.
A given pin on port E will be an output pin if the corresponding PEIORL or PEIORH bit is set to
1, and an input pin if the bit is cleared to 0.
Bits 15 to 6 of PEIORH are reserved. These bits are always read as 0 and should only be written
with 0.
The initial values of PEIORL and PEIORH are H'0000.
Rev. 2.00, 09/04, page 532 of 720
Register
PDCRL2
PDCRL1
PDCRL2
PDCRL1
PDCRL2
PDCRL1
2. The initial value is 1 in the on-chip ROM disabled 8-bit external-expansion mode.
Port E I/O Registers L and H (PEIORL and PEIORH)
Bit
2
2
1
1
0
0
Bit Name
PD2MD1
PD2MD0
PD1MD1
PD1MD0
PD0MD1
PD0MD0
Initial
Value
0
0*
0
0*
0
0*
2
2
2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
PD2 Mode
Select the function of the PD2/D2/SCK2/AUDATA2
pin.
00: PD2 I/O (port)
01: D2 I/O (BSC)
PD1 Mode
Select the function of the PD1/D1/TXD2/AUDATA1
pin.
00: PD1 I/O (port)
01: D1 I/O (BSC)
PD0 Mode
Select the function of the PD0/D0/RXD2/AUDATA0
pin.
00: PD0 I/O (port)
01: D0 I/O (BSC)
10: SCK2 I/O (SCI)
11: AUDATA2 I/O (AUD)*
10: TXD2 output (SCI)
11: AUDATA1 I/O (AUD)*
10: RXD2 input (SCI)
11: AUDATA0 I/O (AUD)*
1
1
1