HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 147

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Break on CPU Data Access Cycle
1. Register settings: UBARH = H'0012
2. Register settings: UBARH = H'00A8
Break on DTC Cycle
1. Register settings: UBARH = H'0076
2. Register settings: UBARH = H'0023
Conditions set:
A user break interrupt occurs when word data is written into address H'00123456.
Conditions set:
A user break interrupt does not occur because the word access was performed on an even
address.
Conditions set:
A user break interrupt occurs when longword data is read from address H'0076BCDC.
Conditions set:
A user break interrupt does not occur because no instruction fetch is performed in the DTC
cycle.
UBARL = H'3456
UBBR = H'006A
UBCR = H'0000
Address: H'00123456
Bus cycle: CPU, data access, write, word
Interrupt requests enabled
UBARL = H'0391
UBBR = H'0066
UBCR = H'0000
Address: H'00A80391
Bus cycle: CPU, data access, read, word
Interrupt requests enabled
UBARL = H'BCDC
UBBR = H'00A7
UBCR = H'0000
Address: H'0076BCDC
Bus cycle: DTC, data access, read, longword
Interrupt requests enabled
UBARL = H'45C8
UBBR = H'0094
UBCR = H'0000
Address: H'002345C8
Bus cycle: DTC, instruction fetch, read
(operand size is not included in conditions)
Interrupt requests enabled
Rev. 2.00, 09/04, page 105 of 720