HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 383

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 12.2 Relationships between N Setting in BRR and Effective Bit Rate B
Notes: B
Table 12.3 shows sample N settings in BRR in normal asynchronous mode. Table 12.4 shows the
maximum bit rate for each frequency in normal asynchronous mode. Table 12.6 shows sample N
settings in BRR in clocked synchronous mode. For details, refer to section 12.4.2, Receive Data
Sampling Timing and Reception Margin in Asynchronous Mode. Tables 12.5 and 12.7 show the
maximum bit rates with external clock input.
Asynchronous mode
(n = 0)
Asynchronous mode
(n = 1 to 3)
Clocked synchronous
mode (n = 0)
Clocked synchronous
mode (n = 1 to 3)
Mode
B
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
Pφ: Peripheral clock operating frequency (MHz)
n : Determined by the SMR settings shown in the following tables.
CKS1
0
0
1
1
0
1
: Effective bit rate (bit/s) Actual transfer speed according to the register settings
: Logical bit rate (bit/s) Specified transfer speed of the target system
SMR Setting
CKS0
0
1
0
1
Bit Rate
B
B
B
B
0
0
0
0
=
=
=
=
32 × 2
4 × 2
32 × 2
4 × 2
Pφ × 10
Pφ × 10
Pφ × 10
Pφ × 10
2n+1
2n+1
2n
2n
× (N + 1)
× (N + 1)
× (N + 1)
× (N + 1)
6
6
6
6
n
0
1
2
3
Error (%) =
Error (%) =
—
—
Error
Rev. 2.00, 09/04, page 341 of 720




B
B
B
B
0
1
0
1
– 1 × 100
– 1 × 100




0